The present invention relates generally to the dissipation of charge build-up along cavities within integrated circuits during etching. More particularly, the present invention relates to methods of dissipating the charge build-up along cavities within integrated circuits and the structure of an integrated circuit that can be used to dissipate the charge build-up.
Successful construction of nano- and microstructures requires reliable and reproducible methods of production. One such nano- or microstructure is a contact hole or trench (i.e., a cavity). Contact hole structures are generally fabricated using wet (crystal anisotrophy) or dry plasma (ion-bombardment anisotrophy) etching. One example of a contact hole formed by dry plasma etching is shaped by etching through an oxide material overlaying a silicon substrate using a hard photoresist mask deposited on top of the oxide material, wherein the etching substantially stops on the underlying substrate. Contact holes have a diameter, also known as width, and a depth. The diameter is referred to as the feature size and tends to decrease with increasing circuit density. The aspect ratio is the ratio of depth to width and tends to increase as the width decreases and depth increases. Modern integrated circuits are scaled with increasingly narrower design rules. In addition, as the width of the etched features decreases, the aspect ratio increases, necessitating a high aspect ratio etch process.
One such high aspect ratio etch process is reactive ion etching. Reactive ion etching is a process whereby a low pressure gas is subjected to a radio frequency electric field in a reaction chamber to form a plasma. A plasma is a gas which contains positive, negative, and neutral atoms, and/or molecules including radicals and a “gas” of emitted photons. The ions and radicals in the plasma that form the etchants are accelerated by an electric field against the material to be etched. The ions/radicals interact with the surface of the atoms or molecules within the material to be etched, forming a volatile by-product which is subsequently removed from the reaction chamber.
If a chemically inert gas, such as argon, is ionized and accelerated to impinge on a substrate surface, material can be removed from the surface of the substrate by momentum transfer, a process similar to sand blasting. This process is used in three distinct modes: sputter etching, ion-beam milling and focused ion beam etching. Sputter etching and broad-ion beam milling use high-energy, inert gas ions (typically Ar+) to dislodge material from the substrate surface, a highly anisotropic etch process. Anisotropic etching may occur when the etch rate is considerably greater in one direction then in another (also known as unidirectional etching). Isotropic etching may refer to etching in all directions at a relatively even rate.
The ion bombardment in reactive ion etching can also result in a charge build-up on cavity surfaces, resulting in damage to the underlying film and semiconductor surface exposed to ion bombardment. For example, the bottom of the contact hole may charge positively while other surfaces charge negatively, thereby creating undesired local electric fields on the mask surface and/or within the contact hole. These local electric fields may deflect the incoming ions causing changes in the trajectory of those ions. This, in turn, results in the contact hole “twisting” during its formation and becoming non-vertical. Further, sidewall charging may also lead to complete etch stoppage in high aspect ratio contact holes. Another related issue associated with the charge build-up along the surfaces is that the contact hole may miss the active area landing region in the underlying substrate due to the twisting of the contact hole during its formation. Therefore, it is important to produce vertically straight contact holes because straight sidewall profiles ensure that the subsequently deposited metal material can properly fill the etched feature and make suitable electrical contact with the active area landing region.
As used herein, “semiconductor substrate” refers to either a base semiconductor (e.g., the lowest layer of a silicon material in a wafer, or a silicon layer deposited on another material, such as silicon on sapphire) or a partially-fabricated integrated circuit having one or more layers or structures formed thereon or regions formed therein. When reference is made to a semiconductor substrate in the following description, various process steps may have been previously used to form or define regions, junctions, or various structures or features and cavities, such as vias, contact openings, high aspect ratio openings, etc., within or on the semiconductor substrate.
FIG. 1 is a cross-sectional view of one example of a semiconductor substrate 10 that has a “twisted” contact hole resulting from charge build-up. A non-vertical contact hole 14 can create many problems. FIG. 2A illustrates one such problem associated with contact hole 14 twisting. The twisted contact hole 14 depicted in FIG. 2A makes only partial contact with the active area landing region 20, resulting in an imperfect contact between subsequently deposited conductive metal within the contact hole 14 and the active area landing region 20. FIG. 2B illustrates one preferred alignment of the contact hole 14 with the active area landing region 20 in which there is no twisting of the contact hole 14 ensuring that the subsequently deposited conductive metal makes suitable contact with the active area landing region 20. FIG. 2C illustrates a contact hole 14 that is so twisted that it completely misses the active area landing region 20 and no contact is made between the contact hole 14 and the active area landing region 20, resulting in the failure of subsequently deposited conductive metal to make a suitable contact with the active area landing region 20.
FIG. 3 provides another view of the potential problems associated with contact hole twisting. FIG. 3 is an overhead view of a semiconductor substrate 15 showing active area 22 and the importance of etching substantially vertical contact holes 16. When there is proper alignment and limited or no twisting of the contact hole 16, the contact holes 16 are positioned within the active area 22. However, when twisting occurs, the contact holes 18 may twist away from the active area 22 and fall outside of the active area 22. These contact holes 18 do not make contact with the active area 22 when the contact holes 18 are filled with conductive metal.
Although FIGS. 1-3 illustrate the problem of twisting in relation to contact holes, twisting can potentially affect any cavity formed using a variety of semiconductor manufacturing processes. For example, the cavity could be a trench, a via, etc.